1. Field of the Invention
The present invention generally relates to a method for generating multiphase pulse width modulation (PWM) signals, in particular, to a digitized method for generating multiphase PWM signals.
2. Description of Related Art
The arithmetic logic unit (ALU) in an earlier central processing unit (CPU) does not perform any complicated logic calculation therefore it does not consume much power and has long response time. Accordingly, the core voltage (VDD—CORE) required by an earlier CPU is usually generated by driving a buck converter through single-phase pulse width modulation (PWM) and then filtering the power supply output by the buck converter. However, the logic calculations executed by the ALUs of today's CPUs have become very complicated; thus, the conventional method for generating CPU core voltage through single-phase PWM has become outdated. Accordingly, a multiphase PWM method is provided, wherein a plurality of buck converters connected to each other in parallel are sequentially driven so that a stable power supply can be provided to a CPU.
As described above, how to turn on a plurality of buck converters, which are connected to each other in parallel, one by one is a major subject of the multiphase PWM method. Generally speaking, a plurality of saw-toothed waves is provided, and the saw-toothed waves are respectively compared with a reference level through phase split so as to generate a plurality of split phase PWM signals. After that, the buck converters connected to each other in parallel are turned on one by one by using these split phase PWM signals. Below, a conventional method for generating three-phase PWM signals will be described as an example of the conventional technique for generating a plurality of split phase PWM signals.
FIG. 1 illustrates a conventional method for generating three-phase PWM signals. Referring to FIG. 1, the duty cycles of the three-phase PWM signals (d)˜(f) are all 50% on and 50% off. In order to generate these three-phase PWM signals (d)˜(f), first, three sawtooth signals (a)˜(c) are provided. The sawtooth signals (a)˜(c) are respectively generated by a triangle wave generator, and the sawtooth signals (a)˜(c) are processed by a RC delay circuit and become three split phase sawtooth signals (a)˜(c). The sawtooth signals (a)˜(c) have the same switch period TSW, and the phase difference between the sawtooth signals (a)˜(c) is a third of the switch period TSW (TSW/3). In addition, the peak voltage of each of the sawtooth signals (a)˜(c) is 1V, and the valley voltage thereof is 0V.
Thereafter, three reference levels d1˜d3 are provided and are respectively compared with the sawtooth signals (a)˜(c). Here it is assumed that when the reference levels d1˜d3 are greater than the sawtooth signals (a)˜(c), the state of the PWM signals (d)˜(f) is on, and when the reference levels d1˜d3 are smaller than the sawtooth signals (a)˜(c), the state of the PWM signals (d)˜(f) is off. Accordingly, the three-phase PWM signals (d)˜(f) are generated based on foregoing assumption.
It has to be mentioned here that the voltage value of foregoing three reference levels d1˜d3 has to be determined according to the duty cycles of the PWM signals (d)˜(f). In other words, when the duty cycles of the PWM signals (d)˜(f) are 50% on and 50% off, the voltage value of the reference levels d1˜d3 is 0.5V. In addition, when the duty cycles of the PWM signals (d)˜(f) are 70% on and 30% off, the voltage value of the reference levels d1˜d3 is 0.7V, and so on. The voltage value of the reference levels d1˜d3 can be changed according to the actual requirement, so that the desired multiphase PWM signals can be generated, and accordingly the buck converters connected to each other in parallel can be turned on sequentially.
As described above, according to a conventional method for generating multiphase PWM signals, a plurality of sawtooth signals are processed by a RC delay circuit so as to generate a plurality of split phase sawtooth signals, and then the split phase sawtooth signals are respectively compared with a reference level to generate the multiphase PWM signals. In other words, in the conventional technique, a plurality of split phase sawtooth signals is provided through a phase delay concept, and the multiphase PWM signals are then generated based on these split phase sawtooth signals. Related techniques are respectively disclosed in U.S. Pat. Nos. 6,628,106, 6,366,069, 6,218,815, and 7,002,325.
However, in all the techniques disclosed in foregoing U.S. patents, the number N of split phases of the PWM signals is restricted, and accordingly, the duty cycle of each phase PWM signal is between 0 and 1/N or between 0 and ½N, wherein N is a positive integer greater than or equal to 3. Thereby, fully on duty cycle cannot be accomplished, and accordingly these techniques can only be applied to buck converters but not in boost converters.